The Gold Standard for Accurate Parasitic Extraction and Signal Integrity Solutions
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60nm and 90nm Interconnect Modeling Challenges. FSA 2004, Design Modeling Workshop. By Ersed Akcasu. |
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Practical Multi-Gigahertz Clocks for ASIC and COT Designs. By Haris Basit, John Wood, and Kenneth Pedrotti. |
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A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings. By Ersed Akcasu, Jerry Tallinger, and Kerem Akcasu. |
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Tools for On-Chip Interconnect Inductance Extraction. By Jerry Tallinger and Haris Basit. |
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Spiral and RF-PASS Three Dimensional Design and Analysis Tools for RF Integrated Circuits. By Ersed Akcasu, Haris Basit, Kerem Akcasu, Tufan Colak and Ibrahim Akcay. |
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A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and their Impact on the Design of Multi-Giga Hertz Processors. By Ersed Akcasu, Onur Uslu, Nagaraj Ns, Tufan Colak, Stephen Hale, and Edmund Soo. |
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Optimization of Metal-Metal Comb-Capacitors for RF Applications. By Jay Pajagopalan and Haris Basit. |
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NET-AN a Full Three Dimensional Parasitic Interconnect Distributed RCL Extractor for Large Full Chip Applications. By Ersed Akcasu, Jesse Lu, Alexander Dalal, Sundari Mitra, Hem Hingarh, and Haris Basit. |
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Case Study of On-Chip Inductance Effects (Extraction and Analysis). By Ersed Akcasu |
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