Morgan Hill, California -
June 2, 2005.
OEA International, Inc. (OEA) announces a major revision to
DP-PLAN[TM], the next-generation dynamic power planning solution for
pre-design of the core power grid on complex SoC designs. In this latest
version, OEA has included a robust color-coded output of the voltage
simulation outputs for user defined time slices and for global supply
violation reporting. In this way the user can quickly identify problem
areas in the layout and implement fixes by adding decoupling capacitors or
changing the power grid. The color-coded display is provided by the OEA
Post-Layout Workshop tool which allows for a global view or zoomed in detail
view showing exact simulated values at any point on the power grid.
DP-PLAN is the only tool
available to correctly and accurately model full on-chip inductance and
inductance coupling effects directly in the simulation of the power network.
At the floorplanning stage, DP-PLAN helps avoid IR drop problems brought
about by high speed switching conditions by finding the problem areas and
allowing you to fix them by changing the grid or specific placement of
by-pass capacitors. It also calculates effective supply impedance from any
point in the network which in turn can be used for detailed critical net
simulations. DP-PLAN's ease-of-use in setting up the power grid design,
fast accurate extraction using NET-AN, and network simulation performance
enables designers to easily identify the power integrity issues early in
Dynamic Core power planning
is a major challenge from the perspectives of both design and verification.
OEA's methodology is based on the true electrical model of the power grid
which includes both inductance and mutual inductance, both of which can have
a significant impact on the networks performance. Other tools have limited
accuracy due to the inability to accurately process the inductive effects of
the power network properly.
Easy Power Grid
floorplanning file allows easy placement of power grid features such as top
level rails, hierarchical blocks, current sources, voltage sources, and
by-pass capacitors. Simulation controls, design rules for checking, and
output parameters are controlled in the same control file as the physical
description of the grid. DP-PLAN also supports multiple power net domains
combined in the same simulation, automatic rail hook-ups by connecting to
nearest same net metal in all directions, automatic via insertion per user
rules, and full flip-chip bump support for voltage source definitions.
DP-PLAN uses the
unparalleled OEA NET-AN extraction engine with the advanced 'Cheetah' 3D
field solver technology for the most accurate parasitic extraction
available. NET-AN, the fastest 3D solver available, quickly extracts huge
power networks including inductance and mutual inductance.
Fast Spice Simulation with
Superior Inductance Support
DP-PLAN includes the new
'PANTHER' Spice simulator for fast and accurate solutions of large coupled
networks. Panther is the only Spice engine capable of solving large
inductively coupled networks which include thousands of mutual inductors.
Panther is run for both transient and AC simulation modes. This allows the
user to not only simulate dynamic voltage variations but also to map
effective impedance to all areas on the chip. Effective impedance
simulation allows the user to find clock and critical path problems due to
voltage supply impedance issues and to help locate by-pass capacitors
required to assure correct operation.
International, Inc., is the industry leader in 3D extraction of
interconnects. OEA’s tools are currently used in the most demanding
extraction and design environments. Some of the world's most advanced design
facilities use OEA tools for detailed analysis and design of high-speed
clocks, buses, I/O rings, and power grids. For additional information call
(408)738-5972, or visit OEA online at
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