The Gold Standard for Accurate Parasitic Extraction and Signal Integrity Solutions



Contact: Jerry Tallinger
VP Marketing & Sales, OEA
(408) 738-5972


Santa Clara, CA – January 10, 2000 - OEA International, Inc. announces the contract completion and delivery of high accuracy design tools for deep-submicron designs to each SEMATECH member. The delivered OEA Chip Parasitic Extraction and Signal Integrity Verification (CPE&SIV) tools are designed to significantly enhance SEMATECH member companies' ability to design VLSIs with geometries down to 130 nanometers.  The OEA tools are designed to be compatible with Chip Hierarchical Design System (CHDS technical data) tool standard being promoted by SEMATECH and its member companies.  OEA is the key contributor in providing high accuracy parasitic extraction for timing calculation and power distribution network analysis tools.   OEA also used its expertise to deliver the first comprehensive study of the effects of on-chip inductance and advise SEMATECH member companies on the need for inductance extraction in VLSI design.

As indicated in the International Technology Roadmap for Semiconductors, feature size will continue to scale down and chip sizes will continue to grow. As this trend continues, interconnect has become the major factor in determining timing and performance in VLSI circuits. It has become necessary to model critical interconnect more accurately in order to meet the needs of timing and signal integrity. OEA, working with SEMATECH, has enhanced five major products, NET-AN a 3-D Critical Net Parasitic Extractor; P-GRID a 3-D Power Distribution Network Analyzer, P-PLAN and RING Designer for Power Distribution Network Floorplanning and Design Rule Analysis, and TECH-AN an IC Process Statistical Analyzer.

High Accuracy Net Parasitic Extraction
NET-AN is a three-dimensional IC field simulator for extracting accurate RCLM SPICE parasitics of selected critical nets on an IC.  NET-AN graphically extracts, builds a 3D model, and simulates a net, tree, or critical path allowing the user or the system to automatically assign nodes. SEMATECH driven enhancements included multi-net capability, Application Program Interface (API) to formula-based full chip extraction tools, enhancements for handling the new copper-based technologies, and further speed enhancements.

IC Process Statistical Analysis Tool
OEA has developed a new innovative product, TECH-AN, which statistically analyzes manufacturing process variations and determines probabilistic variations in electrical RC parasitics. The data can then be used with floorplanners, routers and other extraction tools for performance driven design.

Power Distribution Network Analysis and Floorplanning
P-GRID is used for post-layout analysis of the power or ground interconnect networks on an IC for I/R (Voltage) drop and electromigration violations. P-GRID extracts, builds a 3-D model, and simulates power distribution networks reporting excessive drops in supply voltage or excessively high current density levels that will lead to early chip failure. One of the most important steps in designing a large VLSI is setting up proper design rules for power and ground interconnect. For optimizing the geometric configuration of power and ground rings, internal power rails, and ring voltage source pad locations, OEA has developed P-PLAN. Common problems of ground bounce and simultaneous switching noise on I/O rings are avoided by proper analysis with a new OEA tool called RING Designer.

OEA International, Inc. designs and licenses state-of-the-art signal integrity software for the electronic design automation (EDA) industry. OEA's software is designed to be extremely high performance and handle very complex models with a high degree of accuracy. OEA products are used to substantially increase engineering productivity and first time success in the design of interconnect and packaging technologies for sophisticated electronic systems and integrated circuits. Additional information is available at

International SEMATECH is a non-profit research and development consortium of semiconductor manufacturing companies, including AMD, Conexant, Hewlett-Packard, Hyundai, Infineon Technologies, Intel, IBM, Lucent Technologies, Motorola, Philips, STMicroelectronics, TSMC, and Texas Instruments. The CHDStd effort, having been successfully piloted by International SEMATECH through beta testing, has been moved to the SI2 consortium for implementation with a broader industry constituency.   Additional information is available at

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