The Gold Standard for Accurate Parasitic Extraction and Signal Integrity Solutions



Contact: Jerry Tallinger
VP Marketing & Sales, OEA
(408) 738-5972



Santa Clara, CA - DAC, June 1999 - OEA International, Inc. announces the first release of "CLOCK Designer ", the first clock floorplanning tool which utilizes a full 3-D field solver for RCLK value extraction. CLOCK Designer is a VLSI floorplanning tool for the fast design and optimization of clock networks at the block or full chip level. CLOCK Designer works with the OEA NET-AN 3-D parasitic extraction software, which includes the "Cheetah II" 3-D Laplace/Poisson field solver technology. The program allows for design using gridded, H-tree, or Spine routing strategies. CLOCK Designer can be used to perform a wide variety of what-if scenarios to minimize skew, eliminate delay failures, estimate power and current, and optimize buffer sizes. CLOCK Designer can eliminate days of redesign time due to poor planning of clock routing.

Fast Iteration Times
CLOCK Designer allows easy modifications to the planned clock network layout. Using an easy to modify input control file allows the user to try many alternative strategies and trade-off driver strength with line width and spacing alternatives. Also, the optimal driver and buffer locations can be easily determined to minimize skew and increase the performance of the chip design.

Full Parametric Geometry Creation, 3-D Extraction, SPICE Simulation and Feedback Loop
Using the control file and a technology file, a 3-D model of the clock network is created including all driver/buffers and loads. An accurate RCLK SPICE sub-circuit of the interconnect is extracted using OEA NET-AN 3-D extractor. Then, load and drivers are added, measure statements are included and the full circuit is simulated in SPICE to obtain delays, skew power and current consumption values. This data is then analyzed and the results presented in a report format and also loaded into the OEA PLWS graphic interface for color-coded viewing of the geometry and the predicted delays and skews.

Pricing, Platforms and Availability:
CLOCK Designer runs on all popular Sun and IBM workstations. Available for Beta Site delivery with pricing information upon request.

Other Related OEA International Products:
NET-AN - A three-dimensional IC critical net field simulator for creating very accurate RCL SPICE decks of selected nets on an IC. NET-AN graphically extracts, builds a 3-D model, and simulates a net, tree, or critical path allowing the user or the system to automatically assign nodes.

CELL-AN – A three-dimensional level SPICE extraction that generates a cell or macro sub-circuit with significant RC, S/D resistances and geometry dependent transistor SPICE models.

TECH-AN - An IC process statistical analysis tool that statistically preprocesses technology data for floorplanners, routers and other extraction tools.

Company Profile

OEA International, Inc. designs and licenses state-of-the-art signal integrity software for the electronic design automation (EDA) industry. OEA's software is designed to be extremely high performance and handle very complex models with a high degree of accuracy. OEA products are used to substantially increase engineering productivity and first time success in the design of interconnect and packaging technologies for sophisticated electronic systems and integrated circuits.

METAL, HENRY, PLWS, NET-AN, CELL-AN, TECH-AN, P-GRID, P-PLAN, SPIRAL, Cheetah II, RAM Designer, CLOCK Designer, and RING Designer are trademarks of OEA International, Inc.

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All Rights Reserved