The Gold Standard for Accurate Parasitic Extraction and Signal Integrity Solutions

 

 

 

For more information, contact:

Jerry Tallinger
OEA International, Inc.
408-778-6747
jerry@oea.com

 

 

Free Technical Seminar

Design of RF-PASSIVE Components & Critical Nets

In San Diego on Thursday, December 12, 2002

Morgan Hill, California December 2, 2002.  OEA International, Inc. is sponsoring a FREE technical seminar focused on RF Passive Components and On-chip Critical Net Design and Analysis. This seminar will introduce you to major extraction issues that directly impact the quality of your critical net and passive component design.  It is vitally important that designers understand these issues to make better design tradeoff decisions and achieve design closure with the highest level of confidence. 

During this intensive one-day seminar, you will learn more about:

  • Designing the Right Inductor or Balun for Your Design

  • Accurate Clock Skew Prediction

  • Interconnect Modeling with Inductance

  • Simple but Highly Accurate Substrate Models

  • Incremental Extraction of Critical Paths

  • Ground Bounce and Switching Noise Prediction

  • Low Power Design and Optimizing Power and Ground Distribution

OEA will be hosting this seminar on December 12, 2002 at San Diego Marriott La Jolla from 9:00AM till 5:00PM. The one-day format allows for a more focused agenda that we hope will make it easier for attendees. Presentation materials will be provided as will breakfast and a lunch.

How To Register For The Seminar

To sign-up for the seminar click here, or call Alla Toy at (408) 778-6747 or email alla@oea.com Space is limited. Please sign up ASAP.

 

Seminar Location and Directions

Technical Seminar will be held on Thursday, December 12, 2002 at San Diego Marriott La Jolla from 9:00AM till 5:00PM. Please click here for driving directions.

About OEA International

OEA International, Inc. was formed in 1988 to address demanding IC extraction problems.  The company has secured the extraction accuracy leadership role by working closely with major IC and system companies using the most modern process technologies available.  Through these relationships, the company has applied it 3D extraction expertise to provide a family of critical net design tools, signal integrity analysis tools, and RF component design tools.

High-speed digital designers employing clocks speeds ranging from 300Mhz to several GHz benefit from the company's NET-AN(tm) product's full 3D RCL extraction.  RF/analog designers use RF-PASS(tm), a passive component analysis tool to ensure the most accurate values for on-chip resistors, capacitors, transformers and baluns.  SPIRAL(tm), a spiral inductor synthesis tool automatically delivers a complete physical layout and models for high-Q on-chip inductors.  P-PLAN and P-GRID enable power grid planning and accurate power network IR-drop, electro migration, and current density analysis for custom and cell-based designs. For additional information call (408) 778-6747, or visit OEA online at

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