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OEA INTERNATIONAL BOOSTS NET-AN EXTRACTOR PERFORMANCE BY AN ORDER OF MAGNITUDE
Santa Clara, CA - May 15, 2001 - OEA International, Inc., today announced a 10X performance boost for its popular NET-AN full 3D parasitic extraction tool. The NET-AN tool, long recognized as the fastest and most accurate full 3D extractor in the industry, is now even faster. With this higher extraction speed, designers can extract and analyze several critical nets in less time than it previously took to extract only one. This is particularly important for designers who work with advanced DSM technologies.
OEA achieved this speed boost through innovative advances in its partial-differential field solving algorithms. The NET-AN extractor uses a fully integrated 3D field solver to dynamically extract resistance and capacitance. In addition, it accurately extracts inductance and mutual inductance parasitics - an important capability for delay and skew analysis in high-speed critical nets. Other extraction tools on the market use approximation and formula-based methodologies that are limited to resistance and capacitance, and have much wider error margins than the NET-AN tool. While these less accurate methodologies have a speed advantage over full 3D field solvers, the speed difference is less of a factor with this new release of NET-AN.
"OEA"s NET-AN tool delivers unmatched speed and
accuracy," said Jerry Tallinger, OEA's vice president of sales and marketing.
"Our customers, such as SUN Microsystems and Texas Instruments, have found that DSM
ICs have a greatly increased number of critical nets.
The improved NET-AN speed allows them to maintain the level of accuracy
required within project schedules. "
NET-AN features include:
Fully coupled 3D field solution parasitic extraction. Multi-net simulations produce capacitively coupled, and optionally inductively coupled, distributed SPICE sub-circuit models. These models allow accurate crosstalk and signal integrity simulations.
Single- or multi-net specification. Designers may select and highlight nets for extraction by annotated name, by using the display and mouse, or by using reference GDSII cells. Individual nets, lists of nets, or groups of coupled nets may be specified for extraction. Also, the surrounding net expansion area to be included in the field simulation is specified.
Full-path SPICE circuits using LEF/DEF. When a specified path or tree consists of multiple nets, NET-AN can automatically include the referenced driver, buffer, and load cell SPICE sub-circuits in the main SPICE output file and add the appropriate measure statements. The NET-AN results can then be used in SPICE to calculate accurate delay and skew values in report or SDF formats.
Connectivity based hierarchical graphic interface. OEAs advanced IC graphics tool, Post-Layout WorkShop, handles reading of standard IC data, display of the layout, selection of nets, building 3D models, and display of color-coded displays. It will read and display an entire hierarchical VLSI module from GDSII, including calculating full connectivity, renaming nets, and assigning nodes. Levels of hierarchy can be toggled on and off, and the display can zoom in and out to view as much or as little detail as desired.
Process and device technology definition. Post-Layout WorkShop menus may be used to define and save the process technology for the design, including metal and dielectric thickness and metal process bias values. Material properties that are necessary for accurate extraction, such as dielectric constant and metal resistivities, are also defined. NET-AN recognizes IC devices such as transistors, resistors, and capacitors through flexible device definition menus, and stores the definitions with the process technology. Complex structures such as conformal dielectrics, multi-metal layers, and local interconnect are easily defined.
Batch and interactive graphics interface. With NET-AN designers may operate in either a scriptable batch mode or in a fully interactive graphics mode.
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