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NEW BUS-AN TOOL FROM OEA INTERNATIONAL HELPS ESTABLISH DESIGN RULES FOR NEW PROCESS TECHNOLOGIES
Santa Clara, CA - May 10, 2001 - When establishing design rules for new process technologies, design teams must evaluate various combinations of drivers, buffers, wire lengths, wire sizes, and metal layers to determine parasitic effects on delays and skews. In the past, this has often required the fabrication and measurement of expensive and time-consuming test chips. Today, BUS-AN, a new tool from OEA International, eliminates the need for a test chip by automatically analyzing combinations of buffer and driver sizes when combined with various sizes and lengths of wires on different metal layers. Design teams can use the results of these tests to establish design rules for interconnects, buses, bus drivers, and hierarchical clock trees.
Because BUS-AN eliminates the need for test chips to evaluate process technologies, designers now have the ability to evaluate different technologies in a short period of time, including comparing technologies from different foundries.
"Interconnect parasitic effects determine the success or failure of overall signal integrity in DSM technologies," said Jerry Tallinger, VP of marketing and sales at OEA International. "BUS-AN helps designers establish design rules that accurately predict the delays and skews and control the crosstalk caused by parasitic effects."
Inputs to BUS-AN consist of the process technology file, a control file that specifies the parameters to be evaluated, and a spice file that defines buffer subcircuits. Using these inputs, BUS-AN creates all the necessary buses, shields, neighbors, and crossovergeometry automatically. All ports are added, and BUS-AN then generates GDSII layouts of the circuits for viewing.
BUS-AN then calls NET-AN, OEA's net extraction tool, to extract a fully coupled spice model of the interconnect that includes resistance, capacitance, inductance and mutual inductance.
Using the interconnect spice models generated by NET-AN as inputs, BUS-AN performs a spice simulation of the test circuits to determine skews and delays for the various buffer/driver and interconnect combinations. BUS-AN then generates graphical representations of the results for analysis by the design team. These results provide the information necessary to establish design rules for interconnects, buses, and clock trees.
With the help of BUS-AN, designers can evaluate:
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