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OEA INTERNATIONAL'S NET-AN PROVIDES FULLY AUTOMATED PARASITIC EXTRACTION FOR ASIC DESIGNS
Extracts delays and skews for clock trees and critical paths with extreme accuracy
Santa Clara, CA - January 15, 2001 - OEA International's NET-AN[TM] tool is used by full-custom IC designers to analyze clock skew, interconnect delays, and signal cross-coupling (crosstalk) problems in high-performance microprocessors, communications devices, and other custom ICs. To fit within the ASIC design flow, NET-AN has a new push-button, automated flow that starts with a list of nets and automatically produces delay and skew information. It is far more accurate than competing ASIC tools because it extracts fully distributed RCLM parameters using a 3D field solver, whereas other tools extract only lumped RC using formula-based methods. It generates its results in minutes while running on standard engineering workstations.
"As ASIC designs move up the performance scale and use advanced copper deep sub-micron technologies, the need for an extremely accurate extraction tool like NET-AN increases," said Jerry Tallinger, marketing VP at OEA International. "ASIC designers can no longer rely on conservative vendor rules to get maximum performance from their designs. They need advanced extraction and verification tools to remain competitive."
NET-AN produces more accurate results than competitive products because it provides the highest level of accuracy available for a distributed RCLM model of the interconnect in its true environment. In most ASIC extraction tools, cell geometry is ignored and only "nearest neighbor" is considered. NET-AN, on the other hand, includes all cell geometry within a "sphere of influence" distance from the selected net and extracts accurate and correctly distributed capacitance at every point of the net. Because of its accuracy and thorough analysis, it eliminates the need for a "fudge factor" to compensate for undetected capacitance.
To further improve delay and skew accuracy, NET-AN uses a full Spice simulation in the flow, including the full Spice subcircuits for drivers and loads. In addition, NET-AN is the only ASIC tool to correctly calculate on-chip inductance, including shield return path inductance and coupling.
The power behind this tool comes from OEA's proprietary Cheetah II 3D field solver that is the EDA industry's only seamless full-field solver for full chip net applications.
With NET-AN, ASIC designers can automatically:
· Extract full 3D RCLM parasitics
· Perform a full Spice simulation of a selected net or path, including drivers and nodes
· Analyze an entire multilevel clock tree with all its connected circuits
· Generate SDF for backannotation
· Generate delay report and color-coded graphic outputs
· Insert custom Spice nodes and view waveforms at any point on a net
NET-AN includes a full GDSII viewer that is also used to view color-coded delays and skews. It also includes utilities for manipulating GDSII files.
NET-AN licenses start at $75,000. It is available for immediate delivery.
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